vs-vskt500-..pbf, vs-vskh500-..pbf, vs-vskl500-..pbf www.vishay.com vishay semiconductors revision: 28-apr-17 1 document number: 94420 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 thyristor / diode and thyristor / thyristor (super magn-a-pak power modules), 500 a features ? high current capability ? high surge capability ? industrial standard package ? 3000 v rms isolating voltage with non-toxic substrate ? ul approved file e78996 ? designed and qualified for industrial level ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 typical applications ? motor starters ? dc motor controls - ac motor controls ? uninterruptible power supplies electrical specifications product summary i t(av) , i f(av) 500 a type modules - thyristor, standard package super magn-a-pak circuit configuration two scrs doubler circuit, scr / diode doubler circ uit, positive control, scr / diode doubler circ uit, negative control super magn-a-pak major ratings and characteristics symbol characteristics values units i t(av) , i f(av) t c = 82 c 500 a i t(rms) t c = 82 c 785 a i tsm 50 hz 17.8 ka 60 hz 18.7 i 2 t 50 hz 1591 ka 2 s 60 hz 1452 i 2 t 15 910 ka 2 s v rrm range 800 to 1600 v t stg range -40 to +150 c t j range -40 to +130 voltage ratings type number voltage code v rrm /v drm , maximum repetitive peak reverse voltage v v rsm , maximum non-repetitive peak reverse voltage v i rrm /i drm maximum at t j = t j maximum ma vs-vsk.500 08 800 900 100 12 1200 1300 14 1400 1500 16 1600 1700
vs-vskt500-..pbf, vs-vskh500-..pbf, vs-vskl500-..pbf www.vishay.com vishay semiconductors revision: 28-apr-17 2 document number: 94420 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 on-state conduction parameter symbol test conditions values units maximum average on-state current at case temperature i t(av), i f(av) 180 conduction, half sine wave 500 a 82 c maximum rms on-state current i t(rms) 180 conduction, half sine wave at t c = 82 c 785 a maximum peak, one-cycle, non-repetitive on-s tate surge current i tsm, i fsm t = 10 ms no voltage reapplied sinusoidal half wave, initial t j = t j maximum 17.8 ka t = 8.3 ms 18.7 t = 10 ms 100 % v rrm reapplied 15.0 t = 8.3 ms 15.7 maximum i 2 t for fusing i 2 t t = 10 ms no voltage reapplied 1591 ka 2 s t = 8.3 ms 1452 t = 10 ms 100 % v rrm reapplied 1125 t = 8.3 ms 1027 maximum i 2 t for fusing i 2 t t = 0.1 ms to 10 ms, no voltage reapplied 15 910 ka 2 s low level value or threshold voltage v t(to)1 (16.7 % x x i t(av) < i < x i t(av) ), t j = t j maximum 0.85 v high level value of threshold voltage v t(to)2 (i > x i t(av) ), t j = t j maximum 0.93 low level value on-state slope resistance r t1 (16.7 % x x i t(av) < i < x i t(av) ), t j = t j maximum 0.36 m high level value on-state slope resistance r t2 (i > x i t(av) ), t j = t j maximum 0.32 maximum on-state voltage drop v tm i pk = 1500 a, t j = 25 c, t p = 10 ms sine pulse 1.50 v maximum forward voltage drop v fm i pk = 1500 a, t j = 25 c, t p = 10 ms sine pulse 1.50 v maximum holding current i h t j = 25 c, anode supply 12 v resistive load 500 ma maximum latching current i l 1000 switching parameter symbol test conditions values units maximum rate of rise of turned-on current di/dt t j = t j maximum, i tm = 400 a, v drm applied 1000 a/s typical delay time t d gate current 1 a, di g /dt = 1 a/s v d = 0.67 % v drm , t j = 25 c 2.0 s typical turn-off time t q i tm = 750 a; t j = t j maximum, di/dt = - 60 a/s, v r = 50 v, dv/dt = 20 v/s, gate 0 v 100 200 blocking parameter symbol test conditions values units maximum critical rate of rise of off-state voltage dv/dt t j = 130 c, linear to v d = 80 % v drm 1000 v/s rms insulation voltage v ins t = 1 s 3000 v maximum peak reverse and off-state leakage current i rrm , i drm t j = t j maximum, rated v drm /v rrm applied 100 ma
vs-vskt500-..pbf, vs-vskh500-..pbf, vs-vskl500-..pbf www.vishay.com vishay semiconductors revision: 28-apr-17 3 document number: 94420 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note ? table shows the increment of thermal resistance r thjc when devices operate at different conduction angles than dc triggering parameter symbol test conditions values units maximum peak gate power p gm t j = t j maximum, t p 5 ms 10 w maximum peak average gate power p g(av) t j = t j maximum, f = 50 hz, d% = 50 2.0 maximum peak positi ve gate current +i gm t j = t j maximum, t p 5 ms 3.0 a maximum peak positi ve gate voltage +v gm 20 v maximum peak negati ve gate voltage -v gm 5.0 maximum dc gate curren t required to trigger i gt t j = 25 c, v ak 12 v 200 ma dc gate voltage required to trigger v gt 3.0 v dc gate current not to trigger i gd t j = t j maximum 10 ma dc gate voltage not to trigger v gd 0.25 v thermal and mechanical specifications parameter symbol test conditions values units maximum junction operating temperature range t j -40 to +130 c maximum storage temperature range t stg -40 to +150 maximum thermal resistance, junction to case per junction r thjc dc operation 0.065 k/w maximum thermal resistance, case to heatsink per module r thc-hs mounting surface smooth , flat and greased 0.02 mounting torque 10 % super magn-a-pak to heatsink a mounting compound is recommended and the torque should be rechecked after a period of 3 hours to allow for the spread of the compound 6 to 8 nm busbar to super magn-a-pak 12 to 15 approximate weight 1500 g case style see dimensions - link at the end of datasheet super magn-a-pak r thjc conduction conduction angle sinusoidal conduction rectangular conduction test conditions units 180 0.009 0.006 t j = t j maximum k/w 120 0.011 0.011 90 0.014 0.015 60 0.021 0.022 30 0.037 0.038
vs-vskt500-..pbf, vs-vskh500-..pbf, vs-vskl500-..pbf www.vishay.com vishay semiconductors revision: 28-apr-17 4 document number: 94420 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 1 - current rati ngs characteristics fig. 2 - current rati ngs characteristics fig. 3 - on-state powe r loss characteristics fig. 4 - on-state powe r loss characteristics fig. 5 - maximum non-re petitive surge current fig. 6 - maximum non-re petitive surge current 60 70 80 90 100 110 120 130 0 100 200 300 400 500 600 30 60 90 120 180 average on-state current (a) maximum allowable case temperature (c) conduction angle vsk.500.. series r (dc) = 0.065 k/ w thjc 60 70 80 90 100 110 120 130 0 100 200 300 400 500 600 700 800 900 dc 30 60 90 120 180 average on-state current (a) maximum allowable case temperature (c) conduction period vsk.500.. series r (dc) = 0.065 k/ w thjc 0 100 200 300 400 500 600 700 0 100 200 300 400 500 rm s li m i t conduc tion angle 180 120 90 60 30 maximum average on-state power loss (w) average on-state current (a) vsk.500.. series pe r ju nc t io n t = 1 3 0 c j 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 dc 180 120 90 60 30 rm s li m i t conduction period maximum average on-state power loss (w) average on-state current (a) vsk.500.. series pe r ju n c t i o n t = 1 3 0 c j 7000 8000 9000 10000 11000 12000 13000 14000 15000 16000 110100 numbe r of equa l amp lit ude half cyc le current pulses (n) peak half sine wave on-sta te current (a) init ia l t = 130c @ 60 hz 0.0083 s @ 50 hz 0.0100 s j at any rated load condition and with ra ted v ap p lied fo llowing surg e . rrm vsk.500.. se ries pe r ju n c t i o n 6000 8000 10000 12000 14000 16000 18000 0.01 0.1 1 peak half sine wave on-state current (a) pu lse t ra in dura tion (s) ma ximum non rep etitive surge current versus pulse tra in dura tion. control of conduction may not be maintained. init ia l t = 130c no volta g e rea p plied ra t e d v re a p p l i e d rrm j vsk.500.. series pe r ju n c t i o n
vs-vskt500-..pbf, vs-vskh500-..pbf, vs-vskl500-..pbf www.vishay.com vishay semiconductors revision: 28-apr-17 5 document number: 94420 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - on-state power loss characteristics fig. 8 - on-state power loss characteristics fig. 9 - on-state power loss characteristics 0 20406080100120 maximum allowable ambient temperature (c) r = 0 . 0 7 k / w - d e l t a r 0 . 0 9 k / w 0 . 1 2 k / w 0 .1 6 k / w 0 . 2 k / w 0 . 3 k / w 0 . 4 k / w 0 . 6 k / w t h s a 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 0 100 200 300 400 500 600 700 800 180 120 90 60 30 to t a l rm s o u t p u t c u r r e n t ( a ) maximum total on-state power loss (w) cond uction angle vsk.500.. se rie s pe r m o d u le t = 130c j 020406080100120 maximum allowable ambient temperature (c) r = 0 . 0 1 k / w - d e l t a r 0 . 0 2 k / w 0 . 0 3 k / w 0 . 0 5 k / w 0 . 0 8 k / w 0 . 1 2 k / w 0 . 2 k / w t h s a 0 500 1000 1500 2000 2500 3000 0 200 400 600 800 1000 total output current (a) maximum total power loss (w) 180 (sine) 180 (rect) 2 x vsk.500.. se rie s si n g l e ph a se br i d g e connected t = 130c j 0 20406080100120 maximum allowable ambient temperature (c) r = 0 . 0 1 k / w - d e l t a r 0 . 0 2 k / w 0 . 0 3 k / w 0 . 0 5 k / w 0 . 0 8k / w 0 . 2 k / w t h s a 0 500 1000 1500 2000 2500 3000 3500 4000 4500 0 250 500 750 1000 1250 1500 total output current (a) maximum total power loss (w) 120 (rect) 3 x vsk.500.. se rie s th r e e ph a se br i d g e connected t = 1 3 0 c j
vs-vskt500-..pbf, vs-vskh500-..pbf, vs-vskl500-..pbf www.vishay.com vishay semiconductors revision: 28-apr-17 6 document number: 94420 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 10 - on-state voltage drop characteristics fig. 11 - thermal impedance z thjc characteristics fig. 12 - gate characteristics ordering information table note ? to order the optional hardware go to www.vishay.com/doc?95172 100 1000 10000 0.5 1 1.5 2 2.5 3 3.5 4 4.5 t = 2 5 c j instantaneous on-state current (a) instantaneous on-state voltage (v) t = 1 3 0 c j vsk.500.. se rie s pe r ju n c t io n 0.001 0.01 0.1 0.001 0.01 0.1 1 10 100 sq u a r e w a v e pu l se d u r a t i o n ( s) thjc tr a n si e n t t hermal impedance z (k/w) vsk.500.. series pe r ju n c t i o n st e a d y st a t e v a l u e : r = 0.065 k/ w (dc operation) thjc 0.1 1 10 100 0.001 0.01 0.1 1 10 100 vgd igd (b) (a) tj =2 5 c tj = - 4 0 c (2) (3) in st a n t a n e o u s g a t e c u r r e n t ( a ) instantaneous gate voltage (v) a) recommended load line for b) recommended load line for <=30% rated di/dt : 10v, 10ohms rated di/dt : 20v, 10ohms; tr<=1 s tr<=1 s (1) (1) pgm = 10w, t p = 4ms (2) pgm = 20w, t p = 2ms (3) pgm = 40w, t p = 1ms (4) pgm = 60w, tp = 0.66ms rectangular gate pulse tj = 1 3 0 c vsk.500.. series frequency limited by pg(av) (4) - circuit configuration (see end of datasheet) - current rating - voltage code x 100 = v rrm (see voltage ratings table) - lead (pb)-free device code kt vs-vs 500 - 16 pbf 2 3 4 5 2 1 4 3 5 1 - vishay semiconductors product
vs-vskt500-..pbf, vs-vskh500-..pbf, vs-vskl500-..pbf www.vishay.com vishay semiconductors revision: 28-apr-17 7 document number: 94420 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 circuit configuration circuit description circuit configuration code circuit drawing two scrs doubler circuit kt scr / diode doubler circui t, positive control kh scr / diode doubler circui t, negative control kl links to related documents dimensions www.vishay.com/doc?95283 + 7 (k2) 6 (g2) - 4 (k1) 5 (g1) ~ 1 2 3 vskt... + - 4(k1) 5(g1) ~ 1 2 3 vskh... + 7(k2) 6(g2) - ~ 1 2 3 vskl...
outline dimensions www.vishay.com vishay semiconductors revision: 14-dec-16 1 document number: 95283 for technical questions within your region: diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 super magn-a-pak thyristor/diode dimensions in millimeters (inches) 60.0 (2.36) 48.0 (1.89) 31.0 (1.22) 50.0 (1.97) 44.0 (1.73) 17 (0.67) max. 19 (0.75) m10 fast-on tabs 2.8 x 0.8 (0.11 x 0.03) 17.8 (0.70) 36.4 (1.14) 4.5 (0.20) 54 6 5, 6 = gate 4, 7 = cathode 7 28.0 (1.10) 26.0 (0.98) 26.0 (0.98) 112.0 (4.41) 124.0 (4.88) 149.0 (5.67) 1.0 (0.039) 32 1 ? 6.5 mm 0.3 mm x 4 hole s (typ.) 52 (2.05) 9.9 0.5 (0.39 0.02) 18 (0.71) max. 48 (1.90)
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